This invention relates generally to signal modulation and more specifically to the generation of pulse-width-modulated signals.
In a communication system, data is typically transmitted in the form of modulated signals. Pulse Width Modulation (PWM) is an important category of modulation techniques. PWM is based on the use of a pulsed signal in which pulses of varying width represent different data being transmitted. Pulse width modulated signals also have widespread applications in many sectors of technology other than communications. For example, servo motor controllers, DC/AC converters, switching power supplies and dimming circuits are just some of the applications in which pulse width modulated signals can be used.
The basic blocks include a modulating signal source which is a sine wave generator and a free running sawtooth generator. The frequency of the sawtooth signal is several times higher than that of the sine wave and it is usually derived from a very stable frequency oscillator. The pulse width modulated signal is generated by comparing the amplitude of the sine wave and the sawtooth wave using a high gain voltage comparator.
FIG. 9 is a block diagram of a typical prior art PWM generating circuit 900. The basic components include a modulating signal source 902 which represents the signal to be transmitted by PWM, and a free running sawtooth generator 904. The frequency of the sawtooth signal 912 produced by the sawtooth generator is several times that of the sine wave signal 914. The sawtooth signal is usually derived from a very stable frequency oscillator. The pulse width modulated signal 910 is generated by comparing the amplitude of the sine wave and the sawtooth wave using a high gain voltage comparator 906.
FIGS. 10A–10C illustrate an analog input waveform 1002 applied to a conventional technique for generating PWM signals. The analog input waveform 1002 represents the data to be transmitted. FIG. 10B illustrates a sawtooth waveform 1004 generated by a free running sawtooth generator. FIG. 10C illustrates a pulse width modulated signal 1006 generated by comparing the amplitude of the analog input waveform 1002 and the sawtooth waveform 1004, according to this conventional technique. It can be seen in FIG. 10B that when the amplitude of the analog input waveform 1002 exceeds the amplitude of the sawtooth waveform 1004, the comparator 906 outputs a high level signal shown in FIG. 10C. Otherwise, the comparator outputs a low level signal. Note that a duty cycle can be defined as the ratio of the pulse width (TW) to the pulse period (TP) shown in FIG. 10C.
This technique faces a number of difficulties in implementation. For example, the free running sawtooth generator 904 must be accurately controlled to operate at a frequency several times higher than that of the analog input wavefonn wave 1002. Also, the average amplitude of both the input waveform 1002 and the sawtooth waveform 1004 must be carefully matched. If there is a significant mismatch, the comparator output could be diminished due to a resulting DC component.
Conventional techniques also exist for generating PWM signals where the data to be transmitted is digital data. Typically, such techniques use an oversampling clock in connection with a counter and/or appropriate combinatorial logic to generate a PWM signal. However, the accuracy of the PWM signal is directly dependent upon the oversampling rate provided by oversampling clock. The requirement for an oversampling clock of sufficiently high rate significantly increases the cost of devices implementing such techniques.
U.S. Pat. No. 5,789,992 describes a PWM method using purely digital logic circuit. The method basically generates a series of PWM component signals. These component signals will be operated with the digital word input using AND and OR logic operations to produce a PWM signal that corresponds to the digital word. It can be appreciated that this method requires an oversampling clock in order to produce a sufficiently accurate PWM signal that is useful.
U.S. Pat. No. 6,044,113 describes a circuit and method for generating digital PWM using an oversampling clock signal and Voltage-to-Frequency Conversion (VFC). The VFC converts an analog input signal to produce a digital word. This digital word, along with the oversampling clock, is provided to a counter to generate a PWM signal that is proportional to the digital word.
Clearly, it can be seen that there is room for improvement over prior art PWM techniques.